FPGA Engineer

About Macnica

Macnica Americas, Inc. is the North American division of Macnica Fuji Electronics Holdings, Inc. a $10 billion technology solutions provider with a stronghold in semiconductor distribution. Macnica excels in customizing solutions to client requirements and leveraging skilled engineers to expedite product development without compromising outcomes for our clients.

Learn more about the Macnica team members you’ll be joining!

Job Summary:

The Senior FPGA Engineer is a key member of the engineering team responsible for the design, implementation, verification, and optimization of FPGA and SoC-based solutions for high-performance networking, video, and professional media applications.

This is a hands-on engineering role requiring strong expertise in Verilog/SystemVerilog, FPGA architecture, simulation, timing closure, hardware debugging, and modern AI-assisted engineering workflows. The successful candidate will independently own complex FPGA designs from requirements through implementation and system integration and will work closely with software, hardware, systems, and QA engineers.

Experience with high-speed Ethernet, packet processing, video, and media-over-IP technologies is highly desirable.

Duties/Responsibilities:

• Design, implement, and optimize FPGA RTL using Verilog and SystemVerilog.

• Translate system and product requirements into FPGA architectures, interfaces, and detailed implementation plans.

• Own FPGA features and subsystems from requirements through RTL design, verification, timing closure, hardware bring-up, and system integration.

• Leverage AI-assisted engineering tools where appropriate to accelerate development, verification, debugging, and documentation while maintaining engineering quality, security, and ownership of the resulting design.

• Design high-throughput, low-latency datapaths for networking, video, and streaming applications.

• Implement and optimize Ethernet/IP packet-processing architectures, including packet parsing, buffering, clock-domain crossing, timestamping, and data movement.

• Develop and maintain RTL testbenches and verification environments, including functional simulation, assertions, and coverage where appropriate.

• Develop FPGA constraints, perform static timing analysis, resolve timing violations, and optimize designs for performance, resource utilization, and power.

• Integrate FPGA logic with embedded processors, memories, high-speed I/O, and other system components.

• Develop or modify C/C++ embedded software as required for FPGA bring-up, hardware interaction, testing, and debugging.

• Perform board-level FPGA bring-up and debug using tools such as embedded logic analyzers, oscilloscopes, and protocol analyzers.

• Diagnose complex hardware/software integration issues and drive them to resolution.

• Participate in architecture, RTL, and design reviews and contribute to engineering standards and best practices.

• Collaborate closely with hardware, embedded software, systems, QA, and other engineering teams throughout the product development lifecycle.

• Provide technical guidance and mentoring to less-experienced engineers.

• Produce clear technical documentation covering architecture, interfaces, design decisions, constraints, and verification.

Required Skills/Abilities:

• 5+ years of hands-on FPGA/RTL development experience with significant ownership of production FPGA designs.

• Experience using AI-assisted development tools to improve engineering productivity, including code generation, review, debugging, test development, documentation, and analysis. Ability to critically review and validate AI-generated code and technical output.

• Strong proficiency in Verilog and/or SystemVerilog.

• Strong understanding of synchronous digital design, clock-domain crossing, reset architectures, pipelining, and high-performance FPGA design techniques.

• Demonstrated experience with FPGA constraints, static timing analysis, and timing closure.

• Strong experience with RTL simulation and verification methodologies.

• Experience developing FPGA-based SoC designs and integrating FPGA logic with embedded processors.

• Experience with high-speed Ethernet/IP networking or packet-processing architectures.

• Experience debugging FPGA designs in hardware using tools such as ILA, SignalTap, oscilloscopes, or protocol analyzers.

• Experience with at least one major FPGA development environment, such as AMD/Xilinx Vivado or Altera/Intel Quartus.

• Working knowledge of C/C++ for embedded software, FPGA bring-up, hardware validation, or system debugging.

• Proficiency working within Linux-based engineering and development environments.

• Experience using Git or similar version-control systems.

• Strong analytical and debugging skills spanning FPGA hardware, embedded software, and system-level integration.

• Ability to independently take ownership of complex technical problems and drive them through resolution.

Preferred Qualifications:

• Experience with Ethernet-based professional media or video-over-IP systems.

• Knowledge of RTP, PTP/IEEE 1588, SMPTE ST 2110, AES67, IPMX, or related media-over-IP protocols and standards.

• Experience designing precise hardware timestamping, synchronization, clock-recovery, or other timing-sensitive FPGA systems.

• Experience with FPGA-based video pipelines and video interfaces such as SDI and HDMI.

• Experience with AXI, Avalon, DMA, DDR memory controllers, PCIe, or similar high-speed FPGA interfaces.

• Experience with Pro-AV, broadcast, video, imaging, or other high-bandwidth real-time applications.

• Experience with FPGA build automation and CI/CD workflows.

• Experience taking FPGA designs from initial architecture through production deployment.

• Experience applying AI-assisted development workflows to FPGA/embedded engineering, including RTL and testbench development, verification, build and automation scripts, embedded C/C++, debugging, and technical documentation.

Education and Experience:

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.